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    • 专利摘要:
    Method for producing a transistor on a layer made of a first crystalline semiconductor material for producing a channel, deposited on a dielectric layer, the method comprising the steps of: - epitaxially growing zones into a second semi material conducting on the layer a first crystalline semiconductor material, so as to form source and drain blocks with the layer made of a first crystalline semiconductor material on either side of the channel, the second semi-conductive material conductor having a mesh parameter different from that of the first semiconductor material, - deep amorphization of a part of the zones into a second semiconductor material so as to retain only a layer of second crystalline semiconductor material in surface of the source and drain blocks, and amorphisation of the zones of the layer in a first semiconductor material located under the zones in second material semi-co nducer, - recrystallization of the source and drain blocks so that the second semiconductor material imposes its mesh parameter on the source and drain zones.
    公开号:FR3023972A1
    申请号:FR1456936
    申请日:2014-07-18
    公开日:2016-01-22
    发明作者:Perrine Batude；Frederic Mazen；Shay Reboh；Benoit Sklenard
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    [0001] TECHNICAL FIELD AND STATE OF THE PRIOR ART The present invention relates to a method for manufacturing transistors in the field of microelectronics, more particularly to a method of manufacturing a transistor in which the level of stress applied to the channel is increased. wherein the stress level applied to the transistor channel is increased. In order to improve the performance of the transistors, it is known to apply a constraint to the semiconductor material forming the channel. In the case of an N-type transistor, a tensile stress, also referred to as tensile stress, is applied and in the case of a P-type transistor a compressive stress is applied. This constraint is generated by realizing the source and drain regions in a material that has either a mesh parameter smaller than that of the channel material to obtain a tensile stress or a mesh parameter greater than that of the channel material to obtain a compressive stress. The material of the source and drain regions is epitaxially produced on a layer in which the channel is formed. Such a method is for example described in the document "IEDM 2003 p228 High Performance UTBB FDSOI Devices With 20nm Gay Length for 14nm Node and Beyond" by Q. Liu et al. For example, in the case of a silicon channel, an epitaxy of SiGe makes it possible to apply a compressive stress in the channel and an epitaxy of SiC makes it possible to apply a tensile stress. In the latter case, the amount of substituted carbon incorporated is limited to about 1%, which limits the tensile stress that can be applied.
    [0002] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a process for manufacturing transistors that make it possible to apply stresses, in particular tensiles that are greater, than those obtained by the methods of the state of the art. .
    [0003] The previously stated goal is achieved by a transistor manufacturing method comprising: a step of epitaxially forming zones intended to partially form source and drain blocks on the layer comprising the channel, in a material having a parameter of mesh smaller than that of the channel material in the case where it is desired to apply a compressive stress and a material having a mesh parameter greater than that of the channel material in the case where it is desired to apply a tensile stress, - a partially amorphizing step sources and drain so as to leave a crystalline layer at the top of the access. The residual crystalline layer of the accesses is separated by an amorphous region from the zone of the channel remaining crystalline due to the protection afforded by the gate, and a recrystallization step such that the remaining access crystalline layer mainly imposes its mesh parameter. to the layer containing the channel.
    [0004] Thanks to the invention it is possible to provide zones for forming the SiGe source and drain blocks for applying a tensile stress to the silicon channel. It is then possible to apply stresses greater than those obtained for example by epitaxy of SiC. In other words, a seed crystal is isolated in the epitaxial zones intended to form the source and drain blocks, the latter having a mesh parameter different from that of the material of the channel zone; the germ can then relax and find its own mesh parameter. Subsequently, recrystallization is performed under conditions such that the crystal seed lattice parameter predominates in the source and drain zones.
    [0005] Very advantageously, the N-type transistors can be produced from the same SiGe epitaxy with the method according to the invention and of the P type directly according to the method of the state of the art. The process for manufacturing the transistors is then substantially simplified since the protection required during the various steps during the production of one or the other of the epitaxies is no longer required. Advantageously, the rate of advance of the recrystallization front of the crystalline nucleus is favored with respect to the recrystallization front of the channel zone by choosing a crystalline orientation favoring the direction of the recrystallization front of the crystalline nucleus. The implantation of dopants in the source and drain zones may also make it possible to promote the speed of advancement of the recrystallization front of the crystalline nucleus. The subject of the present invention is therefore a process for producing a transistor on a layer of a first crystalline semiconductor material for producing a channel, deposited on a dielectric layer, the process comprising the steps of: a) growing by at least one epitaxial zone of a second semiconductor material on the layer into a first crystalline semiconductor material, so as to form source and drain blocks with the layer in a first crystalline semiconductor material of on either side of the channel, the second semiconductor material having a mesh parameter different from that of the first semiconductor material, b) deep amorphization of a part of the zones into a second semiconductor material so as to retain only a layer of second crystalline semiconductor material on the surface of the source and drain blocks, and amorphization of at least the zones of the layer in a first material. semiconductor material located under the second semiconductor material regions; and c) recrystallizing the source and drain blocks so that the second semiconductor material imposes its mesh parameter on the source and drain regions.
    [0006] In an advantageous example, the crystalline orientation of the layer in a first semiconductor material is <100>. The method for producing a transistor may comprise a step of producing a gate on the layer made of a first semiconductor material and spacers between the gate and the zones in a second semiconductor material, when the amorphisation step of the zones of the layer in a first semiconductor material, the zones in a first semiconductor material located under the spacers are also made amorphous. A doping step may advantageously take place before, during or after the amorphization step and before the recrystallization step. The dopant (s) may be chosen from phosphorus, arsenic, antimony and boron. For example, the recrystallization temperature of step c) is between 400 ° C and 600 ° C. The thickness of the amorphous zones in a second semiconductor material is preferably between 1 nm and 2 nm. In one example, the realized transistor is an N-type transistor and the second semiconductor material has a larger mesh parameter than the first semiconductor material. The first semiconductor material may then be Si and the second semiconductor material may be SixGey.
    [0007] In a particularly advantageous mode, during step a) two substeps of epitaxial growth take place, a first substep of growth during which a first portion of SixiGeyi is formed, and a second substep during which a second portion of Six2Gey2 is formed, y1 being greater than y2, and wherein, in step b), for a given dose and a given temperature, in step b), at least the zones of the silicon layer located under the SixiGeyi areas are amorphized and y1 and y2 are chosen so that only the first portion of SiXiGey1 among the first Six1Gey1 and second portions Six2Gey2so amorphized. According to another example, the transistor produced is a P-type transistor and in which the second semiconductor material has a smaller mesh parameter than that of the first semiconductor material.
    [0008] The first material and the second material may be III-V semiconductors, for example InGaAs. The layer of a first semiconductor material and the layer of a dielectric material may belong to an SOI substrate.
    [0009] The transistor to be produced may be an FDSOI, for example a FinFet. The subject of the present invention is also a method of producing a plurality of transistors separated by electrical insulating barriers, in which the transistors are produced according to the method according to the invention, and in which the free face of the materials of the electrical insulating barriers is lowered by so as to reduce the contact between the electrical insulating barriers and the zones in a second semiconductor material. The subject of the present invention is also a process for producing a set of N-type and P-type transistors, in which the embodiment of the N-type transistors is carried out according to the method according to the invention and in which, during the production P-type transistors, the source and drain blocks are obtained directly by epitaxial growth of the second semiconductor material simultaneously with the step of epitaxial growth of the second semiconductor material of the process for producing the N-type transistors. Another subject of the present invention is a method for producing a set of N-type and P-type transistors, in which the P-type transistors are produced according to the method according to the invention and in which, during the production of the P-type transistors, N-type transistors, the source and drain blocks are obtained directly by epitaxial growth of the second simultaneous semiconductor material in the step of epitaxial growth of the second semiconductor material of the process for producing P-type transistors. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be better understood on the basis of the description which follows and the drawings in annex on which: FIGS. 1A to 1D are diagrammatic representations of steps of a method according to an exemplary embodiment of the invention; FIGS. 2A to 2C are schematic representations of steps of a production method of FinFet according to an exemplary embodiment of the invention, - Figure 3 is a top view of the Finfet of Figures 2A to 2C. DETAILED DESCRIPTION OF PARTICULAR EMBODIMENTS We will describe a method of manufacturing transistors in which it is desired to apply a tensile stress to the channel in order to produce an N-type transistor.
    [0010] In Figure 1A; an example of a transistor can be seen. The transistor comprises a substrate 2 on which a layer of dielectric material, for example oxide 4, is formed, it is for example of BOX (BOX for "Buried oxide"), having a thickness of the order of 20 nm. A layer of semiconductor material 6 based on crystalline material, silicon in the example described, is formed on the dielectric layer 4 and in contact therewith. The semiconductor layer 6 may have a thickness of, for example, between 3 nm and 50 nm, for example of the order of 6 nm. The substrate 2, the oxide layer 4 and the Si layer 6 may form a SOI (Silicon on Insulator) type substrate.
    [0011] A gate 8 is formed on the layer 6. For this, steps of deposition of a dielectric layer 10 of gate, for example oxide, and one or more layers 12, 14 of material (x) gate, and etching of these layers to achieve a grid pattern 16 facing an area 18 of the semiconductor layer 6 for forming a channel for the transistor, are performed. The gate 16 of the transistor may be formed of a stack comprising a metal layer 12, for example based on TiN, on which rests a semiconductor layer 14, for example based on polysilicon.
    [0012] Insulating spacers 20a, 20b, for example SiXNV-based, are also formed against the lateral flanks of the gate 16, and rest on the semiconductor layer 6. Then, crystalline semiconductor material 22 is grown by epitaxial growth. the semi-conductor layer 6, in order to form with said semiconductor layer 6, blocks 24, 26 crystalline semiconductors intended to form raised source and drain regions based on crystalline semiconductor material arranged on each side; other of the channel zone 18 and spacers 20a, 20b. The thickness of semiconductor material 22 that is grown can be for example of the order of 16 nm. By "elevated" is meant that the blocks 24, 26, which, like the channel zone 18, rest on the insulating layer 4, extend above the semiconductor layer 6 and thus have a greater thickness to that of the channel zone 18. The thickness E (measured in the direction of the z axis of the orthogonal reference [O, x, y, z]) of the blocks 24, 26 may be for example of the order of 21 nm (FIG. 1A). In this example, the semiconductor material 22 is SiGe which has a mesh parameter greater than that of silicon. For the sake of simplicity the SiGe will be designated SiGe in the rest of the application. SiGe contains for example about 30% of Ge.
    [0013] During growth by epitaxy, the SiGe increases according to the mesh parameter of the silicon and then applies to the channel zone 18 a compressive stress. Subsequently, a deep or partial buried amorphization step is applied to the regions 24, 26 so as to form deep zones 24a, 26a of amorphous material from regions 24 and 26 and regions 6a1, 6a2 of amorphous material in the region. layer 6 and so as to maintain a layer of crystalline material 24b, 26b at the free top of the regions 24, 26 or at the top of the access. These remaining crystalline material layers form a seed crystal for subsequent recrystallization. The buried amorphization can be carried out for example according to conditions as described in the document Signamarcheix T. et al., "Fully depleted silicon on insulator MOSFETs on (110) surface for hybrid orientation technologies" SolidState Electronics Volume 59, Issue 1, May 2011. In this document, the amorphization is obtained by implantation of high dose and high energy Si ions. At the end of this amorphization step, the channel zone 18 and the layers 24b, 26b are crystalline. When the partial amorphization step is complete, the SiGe crystalline layers 24b, 26b are isolated from the Si channel region, i.e. they are separated by an amorphous zone. The crystalline layers 24b, 26b can then relax and the SiGe resumes its own mesh parameter. This relaxation is advantageously facilitated because of the raised position of the blocks 24, 26, in particular access zones. It may be provided to heat the assembly to facilitate the relaxation of crystalline layers 24b, 26b. In the example shown in FIG. 1B, the channel zone 18 extends over the entire width of the grid and under the spacers, and the amorphous zones 6a1, 6a2 are in contact with the two lateral faces of the channel zone. 18 at vertical planes P containing the lateral flanks of the spacers that are opposite to the side flanks in contact with the grid. We will see alternatively that amorphization under the spacers is possible. The element thus obtained is shown in FIG. 1B.
    [0014] Alternatively, one could consider performing the amorphization using at least one implantation step. The amorphous implantation of the semiconductor material of the semiconductor regions can be implemented using an electron-donating doping species that can also carry out an N-type doping, or with the aid of a electron-doping dopant species for performing a P-type doping. This implantation can also be carried out so as to dope portions of the semiconductor regions located under the spacers, on either side of the channel zone 18. . Thus, at the same time that renders amorphous renders, one dopes access regions to the channel.
    [0015] To achieve this, it is possible to implement an implantation by means of an inclined beam forming a non-zero angle, or even a zero angle, with respect to a normal to the main plane of the substrate (the principal plane of the substrate being a defined plane by a plane passing through it and parallel to the plane [O, x, y]).
    [0016] Implantation with a dose, for example between 5x1013 and 4x1015, and an angle, for example between 0 ° and 60 ° makes it possible to reach and boost the regions located below the spacers near the channel zone 18. A at the end of the amorphization step, the amorphous zones extend, in a vertical direction, from the upper face of the insulating layer 4, to a given height equal to el and which is less than thickness E of the semiconductor blocks 24, 26. The zones 24a, 26a are surmounted by and in contact with the layers 24b, 26b of crystalline semiconductor material belonging to the semiconductor blocks 24, 26 and whose crystal structure has not impacted by the amorphization step.
    [0017] In a subsequent step, the amorphous zones are recrystallized, for example by annealing. During this step of recrystallization shown diagrammatically in FIG. 1C, two recrystallization fronts appear in each source and drain region: a recrystallization front 24c from the layer 24b and a recrystallization front 18a from a sidewall. the channel area 18; a recrystallization front 26c from the layer 26b and a recrystallization front 18b from the other side of the channel zone 18. The recrystallization is initiated by applying a certain temperature to the element. This temperature is for example between 400 ° C and 600 ° C but it could take place at higher temperatures. In the representation of FIG. 1C, the front 24c, whose displacement is symbolized by the arrow F1, progresses vertically downwards and the front 18a of the channel zone 18, whose displacement is symbolized by the arrow F2, progresses laterally. towards the left; the front 26c progresses vertically downwards and the other front 18b of the channel zone 18 progresses laterally to the right.
    [0018] The recrystallization conditions are such that the SiGe imposes on the Si located below the zones 24a, 26a the SiGe mesh parameter, a tensile stress then applies to the silicon of the channel 18. The element thus obtained is represented on the Figure 1D.
    [0019] For this purpose, it is sought to obtain that the recrystallization fronts 24c, 26c of SiGe come as close as possible to the channel 18 before crossing the fronts 18a, 18b. Preferably, during the amorphization step, the amorphous layers 24a, 26a are very thin so that the recrystallization fronts 24c, 26c are close to the zones 6a1, 6a2 in amorphous silicon. This reduces the distance traveled by the fronts 24c, 26c to begin recrystallizing the silicon. For example, in the case of zones 24, 26 having a thickness after epitaxy of 15 nm on a silicon layer 6 of 6 nm which corresponds to the thickness of the channel 18, a crystalline layer 24b, 26b of 13 nm d is preserved. thickness and amorphous zones 24a, 26a of 2 nm in thickness and amorphous zones in the layer 6 are formed at the accesses on both sides of the channel zone, 6 nm thick. Preferably, the total thickness of amorphous is between 8 nm and 18 nm. Preferably, the thickness of the amorphous layer 24a, 26a is as small as possible and is for example between 1 nm and 2 nm.
    [0020] Also preferably, the thickness of the layer 6 of the channel is low, which makes it possible to slow the progression of the recrystallization fronts 18a, 18b. Very advantageously, by choosing the crystallographic orientation of the crystalline layers, it is possible to favor a direction of crystallization with respect to another.
    [0021] The orientations of the channel 18 and the crystalline zones 24b, 26b are identical since the layers 24b, 26b result from an epitaxial growth on the layer 6 in which the channel 18 is formed. By choosing an orientation of the channel 18 <110> the ratio between the effective recrystallization speed in the vertical direction and the effective recrystallization speed in the horizontal direction is greater than 2. Indeed, the recrystallization speed in the horizontal direction is composed of the recrystallization speed in the direction < 110> which is less than the speed in the direction <100> of an order of two and a speed of recrystallization in the direction <111> which is less than the speed in the direction <100> of a 10.
    [0022] Thus the recrystallization fronts 24c, 26c progress at least twice as fast as the fronts 18a, 18b. Alternatively, it is possible to provide amorphization of at least part of the area below the spacers in contrast to the amorphization shown in Figure 1B. This amorphization is for example obtained by means of an inclined beam. In this case, during recrystallization, the recrystallization fronts of the channel zone have an interface with the oxide layer 10 and an interface with the material of the spacers 20a and 20b, the recrystallization under the spacers is then of the type < 111> whereas the recrystallization of the SiGe front is always of type <100>. The ratio of the speeds is then of the order of 20 in intrinsic silicon zones, the vertical recrystallization front of the Si progressing 20 times faster than the recrystallization front of the Si. The recrystallization rate in the SiGe at the interface 24c depends on the Ge concentration. In addition, the choice of the material of the source and drain zones can make it possible to obtain speeds of the fronts 24c, 26c greater than those of the fronts 18a, 18b. For example, SiGe has a recrystallization rate approximately eight times greater than that of Si in the <100> direction at 550 ° C. for a concentration of Ge of the order of 30%. It is also possible to influence the recrystallization rates by doping. The choice of the type of dopant, and / or the choice of the dopant concentration and / or the choice of the recrystallization temperature make it possible to accelerate or, conversely, to reduce the recrystallization rate. For example, phosphorus, As, Sb, Boron can be used to boost areas to be recrystallized. The dopant concentration to be introduced depends on the temperature at which the recrystallization is carried out. Beyond a certain dopant concentration, the recrystallization rate decreases. This concentration limit depends on the type of dopant and the temperature. Aluminum, Gallium, indium and Bismuth can be used as dopants, but they have a lower solubility in silicon.
    [0023] The doping can be carried out during the epitaxial growth of the regions 24 and 26 by adding to the gas mixture for epitaxy a gas containing the dopant and it is activated during the epitaxy and / or during the amorphization step as has been described above, the dopants being activated during recrystallization and / or after amorphization.
    [0024] The speeds of the recrystallization fronts can be modeled using software, for example the software (Sentaurus Process marketed by Synopsys), the following parameters: prefiers and activation energy of an Arrhenius law for each of the microscopic configurations located on a {100} plane, {110} or {111} are entered in the software to determine the recrystallization rates. Thus, it is possible to determine the evolution of the two recrystallization fronts and thus to choose the values of the various parameters so that the SiGe or any other suitable material imposes its mesh parameter. Moreover, the adjacent transistors are separated by an electrical insulating barrier in order to avoid a short circuit between the transistors. This barrier is designated STI for "Shallow Trench Isolation" in English terminology for "shallow isolation trench". STIs are shown in Figure 1A. When the material of the STI (s) is tensile with respect to the material of the source and drain zones 24, 26, it aids in the relaxation of the material of the source and drain regions deposited by epitaxy.
    [0025] On the other hand, if the material of the STI is compressive with respect to the material of the source and drain regions, it is preferable to reduce or even avoid the contact between the STI and the source and drain regions. For this, the level of the upper face of the STIs can be lowered. In a particularly advantageous mode, the concentration of Ge varies during SiGe growth on the semiconductor layer 6, which makes it possible to locate very precisely the amorphized zone of SiGe and thus the interface between the amorphized zone and the crystalline zone. For this purpose, during the production of the SiGe portions on the Si, a first epitaxial layer formed of SixiGev1 and a second epitaxial layer formed of Six2Gey2, y1 being greater than y2, are produced. The difference in concentration of Ge between the two layers is chosen so that, during amorphization with the same given dose and a given temperature, in addition to the amorphization of Si zones located under the SiGe, only the SixiGeyi layer " rich in Ge "is amorphized in the SiGe portions. The layer of Six2Gey2 then corresponds to the left crystalline zone 24b, 26b and the SixiGeyi layer corresponds to the amorphous zone 24a, 26a. It is therefore possible to carry out a selective amorphization by choosing y1, y2, the dose and the temperature. Thus, the interface between the amorphized zone and the zone remaining crystalline is defined by the concentration of Ge and corresponds to the interface of the two layers. This interface is then very precisely localized and can have a reduced roughness.
    [0026] This selectivity in amorphization is for example described in the document "Amorphization threshold in Si implied strained SiGe alloy rents" TW Simpson et al., EMRS Nov 94, Boston For example, the difference between the Ge concentration of the lower zone and the upper zone is 5%.
    [0027] Those skilled in the art will be able to obtain the experimental curves to determine the concentration difference in Ge, as a function of the value of the dose and the temperature to obtain a selective amorphization. The present invention is particularly suitable for FDSOI (Full-Depleted Silicon On Insulator) transistors, since it has raised source and drain regions. In addition, it uses an SOI substrate, the channel and the source and drain regions being then made on a BOX layer, which is also favorable for obtaining a recrystallization according to the mesh parameter of the predominant SiGe with respect to MOS transistors. using a bulk substrate.
    [0028] The method according to the present invention also applies to fin-shaped field effect transistor (FinFet) transistors. An example of such a method is shown in Figures 2A-2C. In Figure 63, we can see the FinFet seen from above. FIGS. 2A to 2C show views along the sectional planes AA and BB shown schematically in FIG. 3. The same references as those of FIGS. 1A to 1C increased by 100 are used to designate the same elements. For example, the layer in which the channel region is formed is designated 106 and the grid pattern is designated 116. In FIG. 2A, crystalline semiconductor material 122 is grown by epitaxy on the semiconductor layer 106, so that forming with said semiconductor layer 106, 110 blocks 124, 126 crystalline semiconductors for forming source and drain regions based on crystalline semiconductor material disposed on either side of the channel zone 118 and spacers 120a, 120b. In this example, the semiconductor material 122 is SiGe which has a mesh parameter greater than that of silicon. During growth by epitaxy, the SiGe increases according to the silicon mesh parameter and then applies a compressive stress to the channel zone 118. In FIG. 2B, regions 124, 126 are subjected to a deep amorphization step so as to form deep zones 124a, 126a of amorphous material from regions 124 and 126 and regions 106a1, 106a2 of amorphous material in the layer 106 and so as to maintain a layer of crystalline material 124b, 126b at the free top of the regions 124, 126 or at the top of the access. These remaining crystalline material layers form a seed crystal for subsequent recrystallization.
    [0029] At the end of this amorphization step, the channel zone 118 and the layers 124b, 126b are crystalline. During a next step shown in FIG. 2C, the amorphous zones are recrystallized, for example by annealing. During this recrystallization step, two recrystallization fronts schematized by arrows appear in each source and drain region: a recrystallization front 124c from the layer 124b and a recrystallization front 118a from a sidewall of the channel area 118; a recrystallization front 126c from the layer 126b and a recrystallization front 118b from the other side of the channel zone 118.
    [0030] In the representation of FIG. 2C, the front 124c, whose displacement is symbolized by the arrow F1 ', progresses vertically downwards and the front 118a of the channel zone 118, whose displacement is symbolized by the arrow F2', progresses laterally to the left; the front 126c progresses vertically downward and the other front 118b of the channel zone 118 progresses laterally to the right.
    [0031] The recrystallization conditions are such that the SiGe imposes on the Si lying below the zones 124a, 126a the SiGe mesh parameter, a tensile stress then applies to the silicon of the channel 18. The present invention is also of interest for constraining a transistor channel of III-V material. For example, in the case of a transistor on insulator with an InGaAs channel, it will be possible to carry out an epitaxy with a higher concentration of Indium in the epitaxy to have a compressive stress and to use the method according to the invention (amorphization and recrystallization) to create the tensile stress in the NMOS and vice versa. Other materials for the channel and for the source and drain areas may be chosen. In the case of a germanium or SiGe channel, to provide the tensile stress, SiGe epitaxial source and drain zones are produced with a lower Ge concentration than in the channel. Alternatively, to apply compressive stress, GeSn could be used for epitaxy.
    [0032] Thanks to the invention, one can choose the material whose epitaxy is the simplest to achieve, and depending on the compressive or tensile stress provided during epitaxy, the amorphization and recrystallization steps take place on the NMOS or PMOS to apply the other tensile or compressive stress. The invention makes it possible to simplify the simultaneous production of N-type and P-type transistors. In fact, it is advantageously possible to implement an epitaxy of SiGe and more generally of a compressive material to apply at the same time a compressive stress. for producing P-type transistors and a tensile stress for producing N-type transistors. To apply a compressive stress to the channel, only SiGe epitaxy is performed in the case of an Si channel, and to apply a tensile stress. the channel is applied to the method according to the invention. It is then no longer necessary to protect the zones N during epitaxy on the zones P and vice versa, this protection being generally achieved by depositing a nitride film which must then be removed. It is also possible to implement an epitaxy of the same tensile material to apply a tensile stress to make P-type transistors and to apply a compressive stress to make N-type transistors. The method of manufacturing the CMOS is therefore simplified. Nevertheless, a method for producing CMOS implementing two different epitaxies for the N zones and the P zones is not outside the scope of the present invention. For example, it is conceivable to apply the method according to the invention to apply a tensile stress for example from a SiGe epitaxy and to apply the method according to the invention to apply a compressive stress for example from an epitaxy of SiC.20
    权利要求:
    Claims (18)
    [0001]
    REVENDICATIONS1. Method of producing a transistor on a layer (6) of a first crystalline semiconductor material for producing a channel (18), deposited on a dielectric layer (4), the method comprising the steps of: a) growing by at least one epitaxial zone of a second semiconductor material on the layer into a first crystalline semiconductor material (6), so as to form source and drain blocks (24, 26) with the layer in a first crystalline semiconductor material (6) on either side of the channel (18), the second semiconductor material having a mesh parameter different from that of the first semiconductor material, b) deep amorphization of a part (24a, 26a) of the zones in a second semiconductor material so as to retain only one layer (24b, 26b) of second crystalline semiconductor material on the surface of the source and drain blocks (24, 26), and amorphization of at least the zones (6a, 6b) of the layer made of a first semiconductor material (6) located under the zones in second semiconductor material, c) recrystallization of the source and drain blocks (24, 26) so that the second semiconductor material imposes its parameter mesh to the source and drain areas.
    [0002]
    2. A method of producing a transistor according to claim 1, wherein the crystalline orientation of the layer of a first semiconductor material (6) is <100>.
    [0003]
    3. A method of producing a transistor according to claim 2, comprising a step of producing a grid (16) on the layer made of a first semiconductor material and spacers (20a, 20b) between the grid (16). ) and the zones in a second semiconductor material, wherein during the amorphization step of the layers of the layer in a first semiconductor material, the zones in a first semiconductor material located under the spacers are also rendered amorphous.
    [0004]
    4. A method of producing a transistor according to one of claims 1 to 3, wherein a doping step occurs before, during or after the amorphization step and before the recrystallization step.
    [0005]
    5. A method of producing a transistor according to one of claims 1 to 4, wherein the dopant or dopants are selected from phosphorus, arsenic, antimony and boron.
    [0006]
    6. Process for producing a transistor according to one of claims 1 to 5, wherein the recrystallization temperature is between 400 ° C and 600 ° C.
    [0007]
    7. A method of producing a transistor according to one of claims 1 to 6, wherein the thickness of the amorphous zones (24a, 26a) in a second semiconductor material is between 1 nm and 2 nm.
    [0008]
    8. A method of producing a transistor according to one of claims 1 to 7, wherein the transistor is an N-type transistor and wherein the second semiconductor material has a larger mesh parameter than the first one. semiconductor material.
    [0009]
    9. A method of producing a transistor according to claim 8, wherein the first semiconductor material is Si and the second semiconductor material is SixGey.
    [0010]
    10. A method of producing a transistor according to claim 9, wherein during step a) two substeps of epitaxial growth take place, a first sub-step of growth in which a first portion of SixiGeyi is formed. and a second sub-step in which a second portion of Six2Gey2 is formed, y1 being greater than y2, and wherein, in step b), for a given dose and a given temperature, during the step b), at least the areas (6a, 6b) of the silicon layer beneath the SixiGeyi areas are amorphized and y1 and y2 are selected so that only the first portion of SixiGeyi among the first SixiGeyi and second portions Six2Gey2 is amorphized .
    [0011]
    11. A method of producing a transistor according to one of claims 1 to 7, wherein the transistor is a P-type transistor and wherein the second semiconductor material has a mesh parameter smaller than that of the first semiconductor material.
    [0012]
    12. A method of producing a transistor according to one of claims 1 to 8 or 11, wherein the first material and the second material are III-V semiconductors, for example InGaAs.
    [0013]
    13. A method of producing a transistor according to one of claims 1 to 12, wherein the layer of a first semiconductor material and the layer of a dielectric material belong to a SOI substrate.
    [0014]
    14. A method of producing a transistor according to one of claims 1 to 13, wherein the transistor to be produced is a FDSOI.
    [0015]
    15. Process for producing a transistor according to one of claims 1 to 14, wherein the transistor to be produced is a FinFet.
    [0016]
    16. A method of producing a plurality of transistors separated by electrical insulating barriers, wherein the transistors are made according to the method according to one of claims 1 to 15, and wherein the free face of the electrical insulating barrier materials is lowered so as to reduce the contact between the electrical insulating barriers and the zones into a second semiconductor material.
    [0017]
    17. A method of producing a set of N-type and P-type transistors, in which the embodiment of the N-type transistors is made according to the method according to claim 8, 9 or 10 and wherein during the production of the transistors. of the P type, the source and drain blocks are obtained directly by epitaxial growth of the second semiconductor material simultaneously with the step of epitaxial growth of the second semiconductor material of the process for producing the N-type transistors.
    [0018]
    18. A method of producing a set of N-type and P-type transistors, in which the realization of the P-type transistors is carried out according to the method according to claim 11 and wherein during the production of the N-type transistors, the source and drain blocks are obtained directly by epitaxial growth of the second semiconductor material simultaneously with the step of epitaxial growth of the second semiconductor material of the process for producing P20 type transistors.
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    同族专利:
    公开号 | 公开日
    FR3023972B1|2016-08-19|
    US20160020153A1|2016-01-21|
    EP2975646B1|2017-05-10|
    EP2975646A1|2016-01-20|
    US9343375B2|2016-05-17|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US20070045729A1|2005-08-31|2007-03-01|Jan Hoentschel|Technique for forming recessed strained drain/source regions in nmos and pmos transistors|
    US20080070370A1|2006-09-19|2008-03-20|Chii-Ming Wu|Silicide formation with a pre-amorphous implant|
    US20100193882A1|2009-01-30|2010-08-05|Jan Hoentschel|In situ formed drain and source regions including a strain-inducing alloy and a graded dopant profile|
    US20120068193A1|2010-09-21|2012-03-22|International Business Machines Corporation|Structure and method for increasing strain in a device|
    US20130137243A1|2011-11-30|2013-05-30|Chan-Lon Yang|Semiconductor process|
    US20140099763A1|2012-10-08|2014-04-10|Stmicroelectronics, Inc.|Forming silicon-carbon embedded source/drain junctions with high substitutional carbon level|
    FR3009648B1|2013-08-09|2016-12-23|Commissariat Energie Atomique|RECRYSTALLIZATION OF SOURCE BLOCKS AND DRAIN FROM THE TOP|KR102241974B1|2014-09-23|2021-04-19|삼성전자주식회사|Semiconductor devices and methods of manufacturing the same|
    FR3051972B1|2016-05-24|2018-10-12|Commissariat A L'energie Atomique Et Aux Energies Alternatives|METHOD FOR PRODUCING A TRANSISTOR COMPRISING SOURCE AND DRAIN OBTAINED BY SEMICONDUCTOR RECRYSTALLIZATION|
    FR3091619B1|2019-01-07|2021-01-29|Commissariat Energie Atomique|Healing process before transfer of a semiconductor layer|
    US11195914B2|2019-07-26|2021-12-07|Applied Materials, Inc.|Transistor and method for forming a transistor|
    法律状态:
    2015-07-31| PLFP| Fee payment|Year of fee payment: 2 |
    2016-01-22| PLSC| Search report ready|Effective date: 20160122 |
    2016-07-29| PLFP| Fee payment|Year of fee payment: 3 |
    2017-07-31| PLFP| Fee payment|Year of fee payment: 4 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1456936A|FR3023972B1|2014-07-18|2014-07-18|PROCESS FOR PRODUCING A TRANSISTOR IN WHICH THE STRAIN LEVEL APPLIED TO THE CHANNEL IS INCREASED|FR1456936A| FR3023972B1|2014-07-18|2014-07-18|PROCESS FOR PRODUCING A TRANSISTOR IN WHICH THE STRAIN LEVEL APPLIED TO THE CHANNEL IS INCREASED|
    EP15177074.0A| EP2975646B1|2014-07-18|2015-07-16|Method for manufacturing a transistor in which the level of stress applied to the channel is increased|
    US14/802,283| US9343375B2|2014-07-18|2015-07-17|Method for manufacturing a transistor in which the strain applied to the channel is increased|
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